The hardware is based on OEM modules to speed up initial development and to allow users flexibility
in their own implementations. All peripheral devices use USB interfaces for communication with the
The Single Board Computer (SBC) logs and processes time-transfer data. It can also act as an NTP server.
The reference design uses a BeagleBone Black
The Field Programmable Gate Array (FPGA) provides a multi-channel time-interval counter for the measurement of 1 pps signals.
The reference design uses an
Opal Kelly XEM6001
The GPS-disciplined oscillator (GPSDO) provides the core timing signals for the system.
The Jackson Labs LTE Lite has been selected for the reference design.
The GPS timing receiver is used for the GPS common-view comparison. The NVS NV08C is currently being evaluated.